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Thursday, November 12, 2020 | History

1 edition of Implementation of a Configurable Fault Tolerant Processor (CFTP) found in the catalog.

Implementation of a Configurable Fault Tolerant Processor (CFTP)

Implementation of a Configurable Fault Tolerant Processor (CFTP)

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  • 35 Currently reading

Published by Storming Media .
Written in English

    Subjects:
  • TEC008000

  • The Physical Object
    FormatSpiral-bound
    ID Numbers
    Open LibraryOL11845784M
    ISBN 10142351291X
    ISBN 109781423512912

    Hardware Fault Tolerance and Redundancy. Most Realtime systems must function with very high availability even under hardware fault conditions. This article covers several techniques that are used to minimize the impact of hardware faults. Redundancy Schemes. Realtime systems are equipped with redundant hardware modules. A universal set of logic gates in a superconducting quantum circuit is shown to have gate fidelities at the threshold for fault-tolerant quantum computing by the surface code approach, in which. Transistor technology scaling has been the driving force in improving the size, speed, and power consumption of digital systems. As devices approach atomic size, however, their reliability and performance are increasingly compromised due to reduced noise margins, difficulties in fabrication, and emergent nano-scale phenomena. Scaled CMOS devices, in particular, suffer from process variations Author: John A. Frye. MidSTAR-1 is the first implementation of the design. It was commissioned by STP to carry the Internet Communications Satellite (ICSat) Experiment for SSP and the Configurable Fault Tolerant Processor (CFTP) Experiment for Naval Postgraduate School (NPS).


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Implementation of a Configurable Fault Tolerant Processor (CFTP) Download PDF EPUB FB2

The Configurable Fault Tolerant Processor (CFTP) team at Naval Postgraduate School (NPS), Monterey, was created to develop, test, and implement reliable computing solutions for the space environment.

The CFTP team seeks to design reliable circuits using Field Programmable Gate Arrays (FPGA) to include designs that mitigate the radiation hazards posed to FPGAs.

The Configurable Fault Tolerant Processor (CFTP) emulates three identical processors, using Triple Modular Redundancy (TMR) to mitigate SEUs on a radiation tolerant FPGA.

With the reconfigurable capabilities of FPGA technology, as newer processors can be emulated, these new configurations can be uploaded to the satellite as software code. IMPLEMENTATION OF CONFIGURABLE FAULT TOLERANT PROCESSOR (CFTP) EXPERIMENTS Gerald W.

Caldwell Major, United States Marine Corps B.A., Emory & Henry College, Submitted in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE IN ELECTRICAL ENGINEERING from the NAVAL POSTGRADUATE SCHOOL December This paper presents the design and implementation of configurable fault-tolerance techniques for a configurable VLIW processor.

The processor can be configured for 2, 4, or 8 issue-slots with different types of execution functional units (FUs), and its instruction set architecture (ISA) is Cited by: 7.

The Configurable Fault Tolerant Processor (CFTP) team at Naval Postgraduate School (NPS), Monterey, was created to develop, test, and implement reliable computing solutions for the space environment. This paper presents a detailed analysis of the behavior of a novel fault-tolerant bit embedded CPU as compared to a default (non-fault-tolerant) implementation of the same processor during a.

Fault tolerant implementation can be relevant in several contexts. Some examples include the following. (1) Costly analysis of possible scenarios—A fault tolerant mechanism may be preferred in situations which require robustness to mistakes where it is costly for the planner to identify.

Fault-Tolerance-in-Multiple-Processor-Architechture Implementation of a simple fault diagnosis system for a multiple processor architecture. The code is implemented on Octave and implements the Diagnosis Algorithm and Accelerated Algorithm for fault detection.

Design and implementation of fault-tolerant soft processors on FPGAs Abstract: This paper presents a novel hardware mechanism to facilitate the design and implementation of soft processors on FPGAs using the Error-correcting code (ECC)-protected memory and Triple Modular Redundancy (TMR).

Abstract: The susceptibility of on-chip communication links and on-chip routers to faults has guided the research towards focusing on fault-tolerance aspects of 2D and 3D Network-on- Chips (NoCs).

In this paper, we propose Logic-Based Distributed Routing for 3D NoCs (LBDR3D), a scalable, re-configurable and fault-tolerant mechanism, which utilizes only two virtual channels for. An FPGA itself is not a Fault Tolerant component, but with the correct configuration it can emulate and behave as one.

The Configurable Fault Tolerant Processor (CFTP) developed at the Naval Postgraduate School (NPS) was intended to work as a platform for the implementation and testing of designs and experiments for space : Gaspar M.

Perez Casanova. Design and ASIC Implementation of a Reconfigurable Fault-Tolerant ALU for Space Applications. fetchIO. fetchIO is a simple, configurable, fault-tolerant http crawler written in Haskell.

The main features are: Configurable number of concurrent fetcher pipelines; Reuse of http connection (configurable) Fetched HTML is zipped and binaryencoded. Design and implementation of fault-tolerant multi- microcomputer systems D Bernhardt and E Schmitter describe a partially meshed ring structure for multimicrocomputer reliability and fault tolerance realization Distributed computer systems based on a multimicro- computer structure offer the best preconditions to improve the reliability of a system and to realize fault by: 1.

In this thesis, the design, implementation, and verification of a fault-tolerant r-VEX, a softcore processor, is presented, so that it could be used as an attractive alternative to expensive radiation-hardened processors for space-based applications.

r-VEX is a VLIW based, dynamically reconfigurable : Muhammad Usman Saleem. Phase-configurable Based on the 8-issue VLIW, idle issue slots during a whole given program phase (i.e., a sequence of instructions words that always have NOPs in specific issue slots) are used to execute duplicated instructions from other pipelines, and their results are checked.

Consequently, it is a configurable fault toleranceCited by: 6. This paper describes a new fault-tolerant computer architecture based on a "distributed implementation" of a symbol- error correcting code.

In this, as at is called, (N, K) concept the faults are masked by this code. The (N, K) concept is described in detail for N = 4 and K = 2. Soto J., Moreno J.M., Cabestany J. () Description of a Fault Tolerance System Implemented in a Hardware Architecture with Self-adaptive Capabilities.

In: Cabestany J., Rojas I., Joya G. (eds) Advances in Computational Intelligence. IWANN Lecture Notes in Computer Science, vol Springer, Berlin, HeidelbergCited by: 2. Fault tolerant is one of major requirements for embedded systems.

As the embedded systems become more and more complex, more chances for various fault. When design embedded system developer has to handle these faults. Before handling faults designer has to identify and understand the types and nature of is the sources for low dependability, faults can be hardware and : Zhi Wen Xiong, Wen Feng Wang, Hong Zeng.

Implementing a Fault Tolerant Real-Time Operating System EEL Presentation 2 Introduction and Implementation of a fault tolerant resource manager using ARINC and RTEMS 32 bit RISC plasma processor running app.

Unit to decode address associated to taskFile Size: KB. been how we can build fault-tolerant circuits while keep-ing costs low.

In this paper, we present a low-cost fault-tolerant architec-ture for processor protection. Subsection will present related work. Section 2 will present the original DIVA ar-chitecture [1]. Section 3 will present the architecture of our. fault-tolerance features. The fault-tolerant features of these machines were motivated by the local unavailability of reliable components and a high probability of reprisals by the ruling authorities should the machine fail.

Over the past 30 years, a number of fault-tolerant computers have been developed that. Fault tolerance on a system is a feature that enables a system to continue with its operations even when there is a failure on one part of the system.

The system can continue its operations at a reduced level rather than be failing completely. In day to day practical implementation, a fault tolerant system like [ ]. Abstract: In this paper, we describe the design and implementation of a new fault-tolerant RISC-processor architecture suitable for a design framework targeting biomedical implants.

The design targets both soft and hard faults and is original in efficiently combining as well as enhancing classic fault-tolerance by: 6. The LEON4 is the latest implementation of the SPARC V8 architecture by Aeroflex Gaisler, in the form of a synthesizable VHDL model of a bit microprocessor.

As was the case with the previous LEON models, the LEON4 is also highly configurable, and particularly. American Institute of Aeronautics and Astronautics Sunrise Valley Drive, Suite Reston, VA Cited by: and therefore high fault tolerance is possible.

This architecture allows many different re-configuration schemes. One of them, based on the Unix operating system had been described and can be used in an implementation of a “self-repairable”, fault tolerant : A.

Zawada, N. Seed, P. Ivey. Recent research in multi-agent systems incorporate fault tolerance concepts. However, the research does not explore the extension and implementation of such ideas for large scale parallel computing systems.

The work reported in this paper investigates a swarm array computing approach, namely 'Intelligent Agents'. In the approach considered a task to be executed on a parallel computing system. FRG. PROBABlLISTICS FAULT TOLERANT COMPUTER DESIGN -THE HARDWARE IMPLEMENTED FAULT TOLERANT APPROACH c. Goring August Systems Ltd., j enllel" Road, Crall'le)', West Sussex RH 10 2GA, UK Abstract The paper compares the advantages and disadvantages of Hardware Implemented Fault Tolerance (HIFT) to Software Implemented Fault Tolerance (SIFT).Author: C.J.

Goring. The hardware implementation of this algorithm leads to a message passing coprocessor which is allocated at each processor of the array.

No need for high silicon overhead is required for the implementation of the message passing coprocessor. This coprocessor executes only the fault tolerant message passing algorithm presented : G. Sirakoulis, V. Raptis, I. Karafyllidis, Ph. Tsalides, A. Thanailakis. The Configurable Fault Tolerant Processor Project aims to demonstrate the feasibility of using Field Programmable Gate Arrays (FPGAs) for spacecraft computer processing by applying various fault tolerance techniques to the designs.

CFTP provides a valuable testbed for on-orbit evaluation of various fault tolerant concepts. We present a formal approach to implement fault-tolerance in real-time embedded systems. The initial fault-intolerant system consists of a set of independent periodic tasks scheduled onto a set of fail-silent processors connected by a reliable communication : AyavTolga, FradetPascal, GiraultAlain.

Security is a challenging issue in resource-constrained applications, e.g. in an embedded system. This study focused on practical lightweight fault-tolerant strategies for hardware implementation of Advanced Encryption Standard (AES) to mitigate the-reliability issue of secure architectures.

In this work, a-fault-tolerant architecture called configurable fault-tolerant AES (CFTA), and its Author: Saeide Sheikhpour, Ali Mahani, Nasour Bagheri. Fault Tolerance Systems Fault tolerance system is a vital issue in distributed computing; it keeps the system in a working condition in subject to failure.

The most important point of it is to keep the system functioning even if any of its part goes off or faulty [18]-[20]. For a system to be fault tolerant, it is related to dependable Size: KB. Free Online Library: Realtime implementation of neural network augmented fault tolerant flight controllers for an advanced fighter aircraft on a target digital signal processor.(Report) by "International Journal of Applied Engineering Research"; Engineering and manufacturing Actuators Control systems Digital signal processors Military aircraft Neural networks.

This book introduces the main ideas offault diagnosis and fault-tolerant control. It gives a thorough survey of new methods that have been developed in the recent years and demonstrates them with examples.

To the knowledge of the authors, all major aspects of fault-tolerant control are treated for the first time in a single bookFile Size: KB. In one implementation of the systemthe common interface bus is, without limitation, a compact peripheral component interconnect (cPCI) bus.

Hulme et al., "Configurable Fault-Tolerant Processor (CFTP) for Spacecraft Onboard Processing",IEEE. *Cited by: that challenge.

An FPGA itself is not a Fault Tolerant component, but with the correct configuration it can emulate and behave as one. The Configurable Fault Tolerant Processor (CFTP) developed at the Naval Postgraduate School (NPS) is intended to work as a platform for the implementation and verification of designs and experiments forAuthor: Perez Casanova, M Gaspar.

@article{osti_, title = {Fault-tolerant parallel processor}, author = {Harper, R E and Lala, J H}, abstractNote = {This paper addresses issues central to the design and operation of an ultrareliable, Byzantine resilient parallel computer.

Interprocessor connectivity requirements are met by treating connectivity as a resource that is shared among many processing elements, allowing.

I was curious, if there are some best practices to make the scheduled tasks/ windows services fault tolerant and reliable. Edit: I am talking about independent tasks or services which on different servers. and my goal is to make sure that the service will keep running, report any failures and recover from them.

Fault tolerance is the property that enables a system to continue operating properly in the event of the failure of (or one or more faults within) some of its components. If its operating quality decreases at all, the decrease is proportional to the severity of the failure, as compared to a naively designed system, in which even a small failure can cause total breakdown.To design fault tolerance aerospace high reliability microprocessor becomes quite urgent.

This work designed fault tolerance SPARC processor based on a development board. The test on development board has shown that OS UcLinux can run normally on the fault tolerance microprocessor. This paper is organized as : Bao Bin, Wan Min, Wang YunLong.Although the Common Object Request Broker Architecture (CORBA) simplifies the implementation of complex, distributed systems significantly, the support of Role-based security for configurable distributed control systems - IEEE Conference Publication.